This invention relates generally to enclosures for containing logic elements of computing systems and, more specifically, to a double-sided backplane or mother board which enables an enclosure to efficiently handle the increased number of elements.
As computing system evolution has occurred, there have been increases in computing speed, processing power and optional functions. These gains or changes have in turn necessitated larger and increasing numbers of logic elements (e.g., cards or books) required in central electronic complexes (CECs). There are some unsolved problems caused by the greater number of logic elements required.
To a large extent, computing speed is limited by the electrical path length between logic elements. As the number of cards increases and as cards have been made larger, the mechanical pitch or physical distance between cards increases. The increased mechanical pitch equals increased electrical pitch which causes bus length increases and response time increases.
As computing capacity has increased, space has become a premium. A CEC currently needs to be put in smaller, more standard enclosures such as EIA racks. Accommodating the increased card numbers referred to above frequently means resorting to enclosures or logic cages that exceed the horizontal space available in typical racks. Therefore, logic cages must be split and electronically interconnected. Clearly, such "daisy-chaining" of logic cages does nothing to alleviate the electrical path length problem.
As complexity has increased, hardware costs have increased. This is due to the need for multiple cages, additional backplanes or mother boards, added cable, additional connectors, additional cable shielding, etc.
Because a typical CEC wastes significant space in the rack (it is generally much shorter than the rack is deep), an obvious solution would seem to be placing two separate CECs or logic cages back-to-back in a rack. However, this is not practical because the central area where the mother boards or backplanes reside would not be accessible. Further, the CEC to CEC interconnection would not be easily accessible to factory or field personnel. For these reasons, multiple CECs or logic cages typically are mounted one on top of the other, but the result is inefficient use of rack space and inefficient use of hardware.
There have been attempts to address these problems in the prior art. U.S. Pat. Nos. 4,530,033; 4,620,265; 3,668,476 and 3,654,112 are directed to enclosures which might be used to contain logic elements. In particular, U.S. Pat. No. 4,530,033 discloses a single circuit card frame which has molded sidewalls and panels having integral joint and lock means for assembling the frame. However, there is no method suggested to incorporate two frames or cages together. Two additional U.S. Patents which are further representative of prior art enclosures are U.S. Pat. Nos. 4,447,856 and 3,184,645 which are directed to shelf units or separate housings, respectively, wherein the housings or shelf units may be attached together.